The development of modern integrated circuits continues to follow a trend toward a higher density of active components within a single integrated circuit chip, with the performance of the active components also improving with the higher density. To achieve such higher densities and improved performance, the size of transistor features such as gate length in MOS circuits and emitter contact size in bipolar circuits must, of course, be reduced. In addition, however, improved performance of the components also requires reduction of the vertical dimension of certain transistor features. For example, high performance bipolar and BiCMOS (merged bipolar and CMOS) circuits require scaling of the depth of the emitter junction into the base region of the bipolar transistors. First, a shallower emitter junction will provide a steeper doping gradient at the emitter-base junction. Secondly, a shallower emitter junction allows a shallower base region to be used. Since a shallower implant can be more tightly controlled, the reduced depth of the emitter junction allows tight control of a narrow base width.
It is well known, in modern n-p-n bipolar transistors, to form the diffused emitter region by the diffusion of n-type dopant from a doped polysilicon layer which is in contact with the base region via a contact opening through an oxide layer overlying the intrinsic (lightly doped) base region. The depth of the emitter junction of course depends upon the time and temperature of the drive-in anneal, and also upon the impurity species and concentration in the emitter polysilicon. A shallower emitter junction thus can be formed by way of reducing the impurity concentration in the emitter polysilicon. FIG. 1 is a plot, based on SUPREM3 simulation, of the junction depth of the emitter junction for various concentrations of phosphorous dopant in the emitter polysilicon. For identical anneal conditions (e.g., 900 degrees Celsius for 25 minutes), the effect of doping concentration on the junction depth is apparent from FIG. 1.
However, disadvantages arise from such reduction of the impurity concentration in the emitter polysilicon. Since the conductivity of the emitter polysilicon decreases with the impurity concentration, reduced impurity concentration in the emitter polysilicon will result in increased series resistance for the emitter electrode. With the small cross-sectional areas for the emitter polysilicon in high density circuits, further reduction in the conductivity will clearly impact the circuit performance. Furthermore, if the bipolar transistor is in a BiCMOS structure, reduction in the n-type impurity concentration of the emitter electrode (and gate electrodes for p-channel MOS transistors formed from the same polysilicon layer as the emitter polysilicon) can allow significant counterdoping of the emitter polysilicon if exposed to the p-type source/drain implant. Such counterdoping will, of course, further reduce the conductivity of the emitter (and gate) electrodes, and reduce it in such a way that the conductivity will be highly sensitive to the p-type source/drain implant. Even in a purely bipolar structure, such counterdoping of the emitter polysilicon may occur if the extrinsic base implant is performed after the formation of the emitter polysilicon and if the emitter polysilicon is exposed to the extrinsic base implant.
Another approach to the reduction of emitter junction depth is the use of arsenic as the n-type dopant in the emitter polysilicon, rather than phosphorous. Since arsenic diffuses relatively slowly in silicon as compared with phosphorous, the temperature of the drive-in anneal must be increased. As is well known in the art, it is desirable to minimize processing temperatures in order to maintain shallow junction depths, and to minimize lateral diffusion, in other regions of the device. Furthermore, the reduced diffusivity of arsenic makes this dopant more sensitive to interfacial layers which may impede the diffusion, limiting the reproducibility of consistent emitter junction depths.
Yet another approach to reducing the emitter junction depth is the use of rapid thermal processing (sometimes referred to as "rapid thermal annealing" or "RTA") as the emitter drive-in anneal. FIG. 2 is a plot, based on SUPREM3 simulation, of the junction depth versus the polysilicon impurity concentration, after RTA of 30 seconds at 1050 degrees Celsius. While the emitter junction depths are reduced by such an anneal, in a BiCMOS process where the source and drain regions are diffused with the same anneal as the emitter junction, the shallower junction due to the RTA for the emitter will also result for the source and drain regions of the MOS devices. Such shallower junctions may not be desired for the MOS devices on the same chip.
It is therefore an object of this invention to provide a method for fabricating a bipolar transistor where the emitter polysilicon is doped with two types of dopant so that a shallow emitter junction may be formed without reduction of the conductivity of the polysilicon emitter electrode.
It is a further object of this invention to provide such a method where the emitter electrode is relatively insensitive to subsequent implantation of dopant of the opposite conductivity type.
It is a further object of this invention to provide such a process which minimizes the processing temperatures of the emitter diffusion.
It is a further object of this invention to provide such a method which is compatible with CMOS processing, for incorporation into a BiCMOS integrated circuit.
It is a further object of this invention to provide such a method where the diffusion of dopant from the emitter polysilicon can be done with the same anneal step as used to form the source/drain regions in MOS transistors on the same chip.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.